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lt1970a 1 1970afa 2v/div 0v 1970a ta01b 100s/div current limit = 500ma v load , r load = 100 v load , r load = 10 v in , 5v/div typical application description 500ma power op amp with adjustable precision current limit the lt ? 1970a is a 500ma power op amp with precise externally controlled current limiting. separate control voltages program the sourcing and sinking current limit sense thresholds with 1% accuracy. output current may be boosted by adding external power transistors. the circuit operates with single or split power supplies from 5v to 36v total supply voltage. in normal opera- tion, the input stage supplies and the output stage sup- plies are connected (v cc to v + and v ee to v C ). to reduce power dissipation it is possible to power the output stage (v + , v C ) from independent, lower voltage rails. the amplifier is unity-gain stable with a 3.6mhz gain-bandwidth product and slews at 1.6v/s. the lt1970a can drive capacitive and inductive loads directly. open-collector status flags signal current limit circuit activation, as well as thermal shutdown of the amplifier. an enable logic input puts the amplifier into a low power, high impedance output state when pulled low. thermal shutdown and a 800ma fixed current limit protect the chip under fault conditions. the lt1970a is packaged in a 20-lead tssop package with a thermally conductive copper bottom plate to facilitate heat sinking. device power supply (dps) with 500ma adjustable current limit features applications n 500ma minimum output current n independent adjustment of source and sink current limits n 1% current limit accuracy n improved reactive load driving stability n operates with single or split supplies n shutdown/enable control input n open-collector status flags: sink current limit source current limit thermal shutdown n fail-safe current limit and thermal shutdown n 1.6v/s slew rate n 3.6mhz gain-bandwidth product n specified temperature range: C40c to 85c n available in a 20-lead tssop package n automatic test equipment n laboratory power supplies n motor drivers n thermoelectric cooler driver v cc common v ee v + en v C 10k 100pf vc src vc snk isnk isrc sense C sense sense + tsd i out out r cs 1 1/4w trace r 100m trace l 200nh 6k +in 20v lt1970a C5v 20v Cin load esr 0.1 4.7f 1970a ta01 v limit 0v to 5v v in v limit t3 cs i out(max) = l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
lt1970a 2 1970afa absolute maximum ratings supply voltage (v cc to v ee ) ..................................... 36v positive high current supply (v + ) ................... v C to v cc negative high current supply(v C ) ....................v ee to v + ampli? er output (out) ..................................... v C to v + current sense pins (sense + , sense C , filter) ........................... v C to v + logic outputs ( isrc , isnk , tsd ) ....... common to v cc input voltage (Cin, +in) ............ v ee C 0.3v to v ee + 36v input current ......................................................... 10ma current control inputs (vc src , vc snk ) .............. common to common + 7v enable logic input .............................. common to v cc common ....................................................... v ee to v cc output short-circuit duration ......................... inde? nite operating temperature range (note 2).... C40c to 85c speci? ed temperature range (note 3) lt1970ac ................................................ 0c to 70c lt1970ai.............................................. C40c to 85c maximum junction temperature.......................... 150c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) symbol parameter conditions min typ max units power op amp characteristics v os input offset voltage 0c < t a < 70c C40c < t a < 85c l l 200 600 1000 1300 v v v input offset voltage drift (note 4) l C10 C4 10 v/c i os input offset current v cm = 0v l C100 100 na i b input bias current v cm = 0v l C600 C160 na input noise voltage 0.1hz to 10hz 3 v p-p electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. see test circuit for standard test conditions. pin configuration fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 v ee v C out sense + filter sense C v cc Cin +in v ee v ee v + tsd isnk isrc enable common vc src vc snk v ee + C 21 t jmax = 150c, ja = 40c/w (note 8) exposed pad (pin 21) is connected to v ee order information lead free finish tape and reel part marking* package description specified temperature range lt1970acfe#pbf lt1970acfe#trpbf lt1970afe 20-lead plastic tssop 0c to 70c lt1970aife#pbf lt1970aife#trpbf lt1970afe 20-lead plastic tssop C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
lt1970a 3 1970afa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. see test circuit for standard test conditions. symbol parameter conditions min typ max units e n input noise voltage density 1khz 15 nv/ hz i n input noise current density 1khz 3 pa/ hz r in input resistance common mode differential mode 500 100 k k c in input capacitance pin 8 and pin 9 to ground 6 pf v cm input voltage range typical guaranteed by cmrr test l C14.5 C12.0 13.6 12.0 v v cmrr common mode rejection ratio C12v < v cm < 12v l 92 105 db psrr power supply rejection ratio v ee = v C = C5v, v cc = v + = 3v to 30v v ee = v C = C5v, v cc = 30v, v + = 2.5v to 30v v ee = v C = C3v to C 30v, v cc = v + = 5v v ee = C30v, v C = C2.5v to C30v, v cc = v + = 5v l l l l 90 110 90 110 100 130 100 130 db db db db a vol large-signal voltage gain r l = 1k, C12.5v < v out < 12.5v l 100 75 150 v/mv v/mv r l = 100, C12.5v < v out < 12.5v l 80 40 120 v/mv v/mv r l = 10, C5v < v out < 5v, v + = C v C = 8v l 20 5 45 v/mv v/mv v ol output sat voltage low v ol = v out C v C r l = 100, v cc = v + = 15v, v ee = v C = C15v r l = 10, v cc = C v ee = 15v, v + = Cv C = 5v l 1.9 0.8 2.5 v v v oh output sat voltage high v oh = v + C v out r l = 100, v cc = v + = 15v, v ee = v C = C15v r l = 10, v cc = C v ee = 15v, v + = Cv C = 5v l 1.7 1.0 2.3 v v i sc output short-circuit current output low, r sense = 0 output high, r sense = 0 500 C1000 800 C800 1200 C500 ma ma sr slew rate C10v < v out < 10v, r l = 1k 0.7 1.6 v/s fpbw full power bandwidth v out = 10v peak (note 5) 11 khz gbw gain-bandwidth product f = 10khz 3.6 mhz t s settling time 0.01%, v out = 0v to 10v, a v = C1, r l = 1k 8 s current sense characteristics v sense(min) minimum current sense voltage vc src = vc snk = 0v l 0.1 0.1 47 10 mv mv v sense(4%) current sense voltage 4% of full scale vc src = vc snk = 0.2v l 15 20 25 mv v sense(10%) current sense voltage 10% of full scale vc src = vc snk = 0.5v l 45 50 55 mv v sense(fs) current sense voltage 100% of full scale vc src = vc snk = 5v l 495 480 500 500 505 520 mv mv i bi current limit control input bias current vc src , vc snk pins l C1 C0.2 0.1 a i sense C sense C input current 0v < (vc src , vc snk ) < 5v l C500 500 na i filter filter input current 0v < (vc src , vc snk ) < 5v l C500 500 na i sense + sense + input current vc src = vc snk = 0v vc src = 5v, vc snk = 0v vc src = 0v, vc snk = 5v vc src = vc snk = 5v l l l l C500 200 C300 C25 250 C250 500 300 C200 25 na a a a current sense change with output voltage vc src = vc snk = 5v, C12.5v < v out < 12.5v 0.1 % current sense change with supply voltage vc src = vc snk = 5v, 6v < (v cc , v + ) < 18v 2.5v < v + < 18v, v cc = 18v C18v < (v ee , v C ) < C2.5v C18v < v C < C2.5v, v ee = C18v 0.05 0.01 0.05 0.01 % % % %
lt1970a 4 1970afa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. see test circuit for standard test conditions. symbol parameter conditions min typ max units current sense bandwidth 2 mhz r csf resistance filter to sense C l 750 1000 1250 logic i/o characteristics logic output leakage isrc , isnk , tsd v = 15v l 1a logic low output level i = 5ma (note 6) l 0.2 0.4 v logic output current limit 25 ma v enable enable logic threshold l 0.8 1.9 2.5 v i enable enable pin bias current l C1 1 a i supply total supply current v cc , v + and v C , v ee connected l 713 ma i cc v cc supply current v cc , v + and v C , v ee separate l 37 ma i cc(stby) supply current disabled v cc , v + and v C , v ee connected, v enable 0.8v l 0.6 1.5 ma t on turn-on delay (note 7) 10 s t off turn-off delay (note 7) 10 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reli- ability and lifetime. note 2: the lt1970ac is guaranteed functional over the operating tem- perature range of C 40c and 85c. note 3: the lt1970ac is guaranteed to meet specified performance from 0c to 70c. the lt1970ac is designed, characterized and expected to meet specified performance from C40c to 85c but is not tested or qa sampled at these temperatures. the lt1970ai is guaranteed to meet speci- fied performance from C40c to 85c. note 4: this parameter is not 100% tested. note 5: full power bandwidth is calculated from slew rate measurements: fpbw = sr/(2 ? ? v p ) note 6: the logic low output level of pin tsd is guaranteed by correlating the output level of pin isrc and pin isnk over temperature. note 7: turn-on and turn-off delay are measured from v enable crossing 1.6v to the out pin at 90% of normal output voltage. note 8: thermal resistance varies depending upon the amount of pc board metal attached to the device. if the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected. warm-up drift v io vs time input bias current vs v cm total supply current vs supply voltage typical performance characteristics time (100ms/div) 1970a g01 0v v os t n7%*7
common mode input voltage (v) C15 C12 C9 C6 C3 0 3 6 9 12 15 input bias current (na) C100 C120 C140 C160 C180 C200 C220 C240 C260 1970a g02 v s = 15v Ci bias +i bias supply voltage (v) 0 C14 total supply current (ma) C10 C6 C2 14 6 4 8 10 18 1970a g03 10 2 C12 C8 C4 12 4 8 0 26 12 14 16 i cc + i v + i ee + i v C 25c 25c C55c C55c 125c 125c
lt1970a 5 1970afa typical performance characteristics gain bandwidth vs supply voltage gain vs frequency gain vs frequency with c load output impedance disabled output impedance slew rate vs supply voltage supply current vs supply voltage open-loop gain and phase vs frequency phase margin vs supply voltage supply voltage (v) 246 0 supply current (ma) 0.5 1.5 2.0 2.5 14 16 18 4.5 i v + i v C 1870a g04 1.0 81012 20 3.0 3.5 4.0 t a = 25c v cc = v + = Cv ee = Cv C i vcc i vee frequency (hz) 100 1k 10 open-loop gain (db) phase margin (deg) 20 30 40 50 10k 100k 1m 10m 100m 1970a g05 0 C10 C20 C30 60 70 40 50 60 70 80 30 20 10 0 90 100 phase gain total supply voltage (v) 0 40 phase margin (deg) 42 46 48 50 60 54 8 16 20 36 1970a g06 44 56 58 52 412 24 28 32 a v = C1 r f = r g = 1k t a = 25c v out = v s /2 total supply voltage (v) 0 0 gain bandwidth (mhz) 1 3 4 5 8 16 20 36 1970a g07 2 412 24 28 32 a v = 100 frequency (hz) voltage gain (db) 10 C30 0 C10 C20 10k 1m 10m 1970a g08 C40 100k v s = 5v a v = 1 v s = 15v frequency (hz) voltage gain (db) 10 C30 0 C10 C20 10k 1m 10m 1970a g09 C40 100k 30nf 10nf 1nf 0nf v s = 15v a v = 1 frequency (hz) 1k 10k 0.001 output impedance () 0.1 100 100k 1m 10m 100m 1970a g10 0.01 1 10 v s = 15v a v = 100 a v = 1 a v = 10 frequency (hz) 1k 1 output impedance () 100 100k 600k 10k 100k 1m 10m 100m 1970a g11 10 1k 10k v s = 15v v enable = 0.8v supply voltage (v) 4 slew rate (v/s) 1.7 10 1970a g12 1.4 1.2 68 12 1.1 1.0 1.8 1.6 1.5 1.3 14 16 18 falling rising a v = C1 r f = r g = 1k t a = 25c
lt1970a 6 1970afa typical performance characteristics small-signal response, a v = 1 small-signal response, a v = C 1 output overdriven % overshoot vs c load undistorted output swing vs frequency full range current sense transfer curve slew rate vs temperature large-signal response, a v = 1 large-signal response, a v = C 1 temperature (c) C50 C25 0 slew rate (v/s) 1.0 2.5 0 50 75 1970a g13 0.5 2.0 1.5 25 100 125 v s = 15v falling rising 20s/div 1970a g14 0v 10v C10v 5v/div r l = 1k 20s/div r l = 1k c l = 1000pf 1970a g15 0v 10v C10v 5v/div 500ns/div 1970a g16 20mv/div r l = 1k 2s/div 1970a g17 20mv/div r l = 1k c l = 1000pf 200s/div 1970a g18 v out 5v/div 0v 0v v in 5v/div v s = 5v a v = 1 c load (pf) 10 0 overshoot (%) 40 50 60 100 1k 10k 1970a g19 30 20 10 v s = 15v a v = 1 a v = C1 frequency (hz) 100 0 output swing (v p-p ) 20 25 30 1k 10k 100k 1970a g20 15 10 5 v s = 15v a v = C5 1% thd v csnk = v csrc (v) 0 v sense (mv) 100 300 500 4 1970a g21 C100 C300 0 200 400 C200 C400 C500 1 2 3 5 sourcing current sinking current
lt1970a 7 1970afa typical performance characteristics safe operating area output stage quiescent current vs supply voltage control stage quiescent current vs supply voltage supply current vs supply voltage in shutdown low level current sense transfer curve logic output level vs sink current (output low) maximum output current vs temperature v csnk = v csrc (mv) 0 v sense (mv) 5 15 25 200 1970a g22 C5 C15 0 10 20 C10 C20 C25 50 25 100 75 150 175 225 125 250 sourcing current sinking current sink current (ma) 0.001 0.4 logic output voltage (v) 0.5 0.6 0.7 0.8 0.01 0.1 1 10 100 1970a g23 0.3 0.2 0.1 0 0.9 1.0 v + = 15v v C = C15v 125c 25c C55c temperature (c) C75 output current (ma) 800 1200 125 1970a g24 400 0 C25 25 75 C50 0 50 100 1600 600 1000 200 1400 v + = 15v v C = C15v source sink supply voltage (v) 0 0 i out peak (ma) 200 400 600 800 10 20 30 40 1970a g25 1000 1200 515 25 35 i out at 10% duty cycle supply voltage (v) 0 output stage current (ma) C10 C6 C2 6 4 8 10 18 1970a g26 10 2 C8 C4 4 8 0 26 12 14 16 i v + i v C 25c 25c C55c C55c 125c 125c supply voltage (v) 0 supply current (ma) C5 C3 C1 3 4 8 10 18 1970a g27 5 1 C4 C2 2 4 0 26 12 14 16 i cc i ee 25c 25c C55c C55c 125c 125c supply voltage (v) 0 total supply current, i cc + i v + (a) 400 500 600 16 1970a g28 300 200 0 4 8 12 218 6 10 14 100 800 700 85c 25c C55c v enable = 0v
lt1970a 8 1970afa pin functions v ee (pins 1, 10, 11, 20, 21): minus supply voltage. v ee connects to the substrate of the integrated circuit die, and therefore must always be the most negative voltage ap- plied to the part. decouple v ee to ground with a low esr capacitor. v ee may be a negative voltage or it may equal ground potential. any or all of the v ee pins may be used. unused v ee pins must remain open. v C (pin 2): output stage negative supply. v C may equal v ee or may be smaller in magnitude. only output stage current flows out of v C , all other current flows out of v ee . v C may be used to drive the base/gate of an external power device to boost the amplifiers output current to levels above the rated 500ma of the on-chip output devices. unless used to drive boost transistors, v C should be decoupled to ground with a low esr capacitor. out (pin 3): amplifier output. the out pin provides the force function as part of a kelvin sensed load connection. out is normally connected directly to an external load cur- rent sense resistor and the sense + pin. amplifier feedback is directly connected to the load and the other end of the current sense resistor. the load connection is also wired directly to the sense C pin to monitor the load current. the out pin is current limited to 800ma typical. this current limit protects the output transistor in the event that connections to the external sense resistor are opened or shorted which disables the precision current limit function. sense + (pin 4): positive current sense pin. this lead is normally connected to the driven end of the external sense resistor. sourcing current limit operation is activated when the voltage v sense (v sense + C v sense C) equals 1/10 of the programming control voltage at vc src (pin 13). sink- ing current limit operation is activated when the voltage v sense equals C1/10 of the programming control voltage at vc snk (pin 12). filter (pin 5): current sense filter pin. this pin is normally not used and should be left open or shorted to the sense C pin. the filter pin can be used to adapt the response time of the current sense amplifiers with a 1nf to 100nf capacitor connected to the sense C input. an internal 1k resistor sets the filter time constant. sense C (pin 6): negative current sense pin. this pin is normally connected to the load end of the external sense resistor. sourcing current limit operation is activated when the voltage v sense (v sense + C v sense C) equals 1/10 of the programming control voltage at vc src (pin 13). sink- ing current limit operation is activated when the voltage v sense equals C1/10 of the programming control voltage at vc snk (pin 12). v cc (pin 7): positive supply voltage. all circuitry except the output transistors draw power from v cc . total supply voltage from v cc to v ee must be between 3.5v and 36v. v cc must always be greater than or equal to v + . v cc should always be decoupled to ground with a low esr capacitor. Cin (pin 8): inverting input of amplifier. Cin may be any voltage from v ee C 0.3v to v ee + 36v. Cin and +in remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. care must be taken to ensure that Cin or +in can never go to a volt- age below v ee C 0.3v even during transient conditions or damage to the circuit may result. a schottky diode from v ee to Cin can provide clamping if other elements in the circuit can allow Cin to go below v ee . +in (pin 9): noninverting input of amplifier. +in may be any voltage from v ee C 0.3v to v ee + 36v. Cin and +in remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. care must be taken to ensure that Cin or +in can never go to a volt- age below v ee C 0.3v even during transient conditions or damage to the circuit may result. a schottky diode from v ee to +in can provide clamping if other elements in the circuit can allow + in to go below v ee .
lt1970a 9 1970afa pin functions vc snk (pin 12): sink current limit control voltage in- put. the current sink limit amplifier will activate when the sense voltage between sense + and sense C equals C1.0 ? v vcsnk /10. vc snk may be set between v common and v common + 6v. the transfer function between vc snk and v sense is linear except for very small input voltages at vc snk < 60mv. v sense limits at a minimum set point of 4mv typical to ensure that the sink and source limit amplifiers do not try to operate simultaneously. to force zero output current, the enable pin can be taken low. vc src (pin 13): source current limit control voltage input. the current source limit amplifier will activate when the sense voltage between sense + and sense C equals v vcsrc /10. vc src may be set between v common and v common + 6 v . the transfer function between vc src and v sense is linear except for very small input voltages at vc src < 60m v . v sense limits at a minimum set point of 4mv typical to ensure that the sink and source limit amplifiers do not try to operate simultaneously. to force zero output current, the enable pin can be taken low. common (pin 14): control and enable inputs and flag outputs are referenced to the common pin. common may be at any potential between v ee and v cc C 3 v . in typical applications, common is connected to ground. enable (pin 15): enable digital input control. when taken low this ttl-level digital input turns off the ampli- fier output and drops supply current to less than 1ma. use the enable pin to force zero output current. setting vc snk = vc src = 0v allows i out = 4mv/r sense to flow in or out of v out . isrc (pin 16): sourcing current limit digital output flag. isrc is an open-collector digital output. isrc pulls low whenever the sourcing current limit amplifier assumes control of the output. this pin can sink up to 10ma of current. the current limit flag is off when the source current limit is not active. isrc , isnk and tsd may be wired or together if desired. isrc may be left open if this function is not monitored. isnk (pin 17): sinking current limit digital output flag. isnk is an open-collector digital output. isnk pulls low whenever the sinking current limit amplifier assumes control of the output. this pin can sink up to 10ma of current. the current limit flag is off when the source current limit is not active. isrc , isnk and tsd may be wired or together if desired. isnk may be left open if this function is not monitored. tsd (pin 18): thermal shutdown digital output flag. tsd is an open-collector digital output. tsd pulls low whenever the internal thermal shutdown circuit activates, typically at a die temperature of 160c. this pin can sink up to 10ma of output current. the tsd flag is off when the die tem- perature is within normal operating temperatures. isrc , isnk and tsd may be wired or together if desired. isnk may be left open if this function is not monitored. thermal shutdown activation should prompt the user to evaluate electrical loading or thermal environmental conditions. v + (pin 19): output stage positive supply. v + may equal v cc or may be smaller in magnitude. only output stage current flows through v + , all other current flows into v cc . v + may be used to drive the base/gate of an external power device to boost the amplifiers output current to levels above the rated 500ma of the on-chip output devices. unless used to drive boost transistors, v + should be decoupled to ground with a low esr capacitor. exposed pad (pin 21): the exposed backside of the pack- age is electrically connected to the v ee pins on the ic die. the package base should be soldered to a heat spreading pad on the pc board that is electrically connected to v ee .
lt1970a 10 1970afa block diagram and test circuit applications information the lt1970a power op amp with precision controllable current limit is a flexible voltage and current source module. the drawing on the front page of this data sheet is representative of the basic application of the circuit, however many alternate uses are possible with proper understanding of the subcircuit capabilities. circuit description main operational amplifier subcircuit block gm1, the 1x unity-gain current buffer and output transistors q1 and q2 form a standard op- erational amplifier. this amplifier has 500ma current output capability and a 3.6mhz gain-bandwidth product. most applications of the lt1970a will use this op amp in the main signal path. all conventional op amp circuit configurations are supported. inverting, noninverting, filter, summation or nonlinear circuits may be implemented in a conventional manner. the output stage includes current limiting at 800ma to protect against fault conditions. the input stage has high differential breakdown of 36v minimum between Cin and +in. no current will flow at the inputs when differential input voltage is present. this feature is important when the precision current sense amplifiers i sink and i src become active. current limit amplifiers amplifier stages i sink and i src are very high transcon- ductance amplifier stages with independently controlled offset voltages. these amplifiers monitor the voltage between input pins sense + and sense C which usually sense the voltage across a small external current sense resistor. the transconductance amplifiers outputs con- nect to the same high impedance node as the main input stage gm1 amplifier. small voltage differences between sense + and sense C , smaller than the user set vc snk /10 3 19 7 9 8 17 16 18 15 12 13 C + C + C + i snk 1970atc r fil 1k r cs 1 r load 1k i src d2 d1 1 = q1 q2 4 5 6 2 gm1 enable common vc src vc src vc snk 5v 15v vc snk isrc isnk Cin v in r g 1k +in enable tsd 14 v cc v + 15v C15v out sense + filter sense C v C v ee 1, 10, 11, 20 10k 10k 10k r f 1k v src + C v snk + C + C
lt1970a 11 1970afa applications information and vc src /10 in magnitude, cause the current limit ampli- fiers to decouple from the signal path. this is functionally indicated by diodes d1 and d2 in the block diagram. when the voltage v sense increases in magnitude sufficient to equal or overcome one of the offset voltages vc snk /10 or vc src /10, the appropriate current limit amplifier becomes active and because of its very high transconductance, takes control from the input stage, gm1. the output current is regulated to a value of i out = v sense /r sense = (vc src or vc snk )/(10 ? r sense ). the time required for the current limit amplifiers to take control of the output is typically 4s. linear operation of the current limit sense amplifier occurs with the inputs sense + and sense C ranging be- tween v cc C 1.5v and v ee + 1.5 v . most applications will connect pins sense + and out together, with the load on the opposite side of the external sense resistor and pin sense C . feedback to the inverting input of gm1 should be connected from sense C to C in. ground side sensing of load current may be employed by connecting the load between pins out and sense + . pin sense C would be connected to ground in this instance. load current would be regulated in exactly the same way as the conventional connection. however, voltage mode accuracy would be degraded in this case due to the voltage across r sense . creative applications are possible where pins sense + and sense C monitor a parameter other than load current. the operating principle that at most one of the current limit stages may be active at one time, and that when active, the current limit stages take control of the output from gm1, can be used for many different signals. current limit threshold control buffers input pins vc snk and vc src are used to set the response thresholds of current limit amplifiers i sink and i src . each of these inputs may be independently driven by a voltage of 0v to 5v above the common reference pin. the 0v to 5v input voltage is attenuated by a factor of 10 and applied as an offset to the appropriate current limit amplifier. ac signals may be applied to these pins. the ac bandwidth from a v c pin to the output is typically 2mhz. for proper operation of the lt1970a, these control inputs cannot be left floating. for low v cc supply applications it is important to keep the maximum input control voltages, vc src and vc snk , at least 2.5v below the v cc potential. this ensures linear control of the current limit threshold. reducing the current limit sense resistor value allows high output current from a smaller control voltage which may be necessary if the v cc supply is only 5v. the transfer function from v c to the associated v os is linear from about 0.1v to 5v in, or 10mv to 500mv at the current limit amplifier inputs. an intentional nonlinear- ity is built into the transfer functions at low levels. this nonlinearity ensures that both the sink and source limit amplifiers cannot become active simultaneously. simul- taneous activation of the limit amplifiers could result in uncontrolled outputs. as shown in the typical performance characteristics curves, the control inputs have a hockey stick shape, to keep the minimum limit threshold at 4mv for each limit amplifier. figure 1 illustrates an interesting use of the current sense input pins. here the current limit control ampli- fiers are used to produce a symmetrically limited output voltage swing. instead of monitoring the output current, the output voltage is divided down by a factor of 20 and applied to the sense + input, with the sense C input grounded. when the threshold voltage between sense + and sense C (v clamp /10) is reached, the current limit stage takes control of the output and clamps it a level of 2 ? v clamp . with control inputs vc src and vc snk tied together, a single polarity input voltage sets the same + and C output limit voltage for symmetrical limiting. in this circuit the output will current limit at the built-in fail-safe level of typically 800ma. enable control the enable input pin puts the lt1970a into a low sup- ply current, high impedance output state. the enable pin responds to ttl threshold levels with respect to the common pin. pulling the enable pin low is the best way to force zero current at the output. setting vc snk = vc src = 0v allows the output current to remain as high as 4mv/r sense .
lt1970a 12 1970afa applications information figure 2. using the enable pin vc src common v ee vc snk v C filter v + 12v en v cc isnk isrc sense C sense + tsd out +in 5v 0v 5v enable disable v in lt1970a C12v Cin r s 1 r l 10 1970a f02 r g 10k r f 10k en 10v/div 0v v out 1v/div 5s/div 0v v in = 0.5v v in = C0.5v in applications such as circuit testers (ate), it may be preferable to apply a predetermined test voltage with a preset current limit to a test node simultaneously. the enable pin can be used to provide this gating action as shown in figure 2. while the lt1970a is disabled, the load is essentially floating and the input voltage and current limit control voltages can be set to produce the load test levels. enabling the lt1970a then drives the load. the lt1970a enables and disables in just a few microseconds. the actual enable and disable times at the load are a function of the load reactance. operating status flags the lt1970a has three digital output indicators; tsd , isrc and isnk . these outputs are open-collector drivers referred to the common pin. the outputs have 36v ca- pabilities and can sink in excess of 10ma. isrc and isnk indicate activation of the associated current limit amplifier. the tsd output indicates excessive die temperature has caused the circuit to enter thermal shutdown. the three digital outputs may be wire ord together, monitored individually or left open. these outputs do not affect circuit operation, but provide an indication of the present operational status of the chip. figure 1. symmetrical output voltage limiting vc src common v ee vc snk v C filter v + 12v en v cc isnk isrc sense C sense + tsd out +in r3 3k 80mv to 10v C80mv to C10v clamp reached output clamps at 2 w v clamp v clamp ov to 5v v in lt1970a C12v Cin r1 21.5k r l 1970a f01 r2 1.13k r f r g for slow varying output signals, the assertion of a low level at the current limit output flags occurs when the current limit threshold is reached. for fast moving signals where the lt1970a output is moving at the slew limit, typically 1.6v/s, the flag assertion can be somewhat premature at typically 75% of the actual current limit value. the operating status flags are designed to drive leds to provide a visual indication of current limit and thermal conditions. as such, the transition edges to and from the active low state are not particularly sharp and may exhibit some uncertainty. adding some positive feedback to the current limit control inputs helps to sharpen these transitions. with the values shown in figure 3, the current limit thresh- old is reduced by approximately 0.5% when either current limit status flag goes low. with sharp logic transitions, the status outputs can be used in a system control loop to take protective measures when a current limit condition is detected automatically.
lt1970a 13 1970afa applications information figure 3. adding positive feedback to sharpen the transition edges of the current limit status flags vc src common v ee vc snk v C filter v + 12v i source flag when current limit is flagged, i limit treshold is reduced by 0.5% i sink flag en v cc isnk isrc sense C sense + tsd out +in v in lt1970a C12v Cin r s 1 r l 1970a f03 r g r f r2 100 r1 100 current limit control voltage (0.1v to 5v) r4 20k r3 20k the current limit status flag can also be used to produce a dramatic change in the current limit value of the ampli- fier. figure 4 illustrates a snap-back current limiting characteristic. in this circuit, a simple resistor network initially sets a high value of current limit (500ma). the circuit operates normally until the signal is large enough to enter current limit. when either current limit flag goes low, the current limit control voltage is reduced by a factor of 10. this then forces a low level of output current (50ma) until the signal is reduced in magnitude. when the load current drops below the lower level, the current limit is then restored to the higher value. this action is similar to a self resettable fuse that trips at dangerously high current levels and resets only when conditions are safe to do so. thermal management minimizing power dissipation the lt1970a can operate with up to 36v total supply volt- age with output currents up to 500ma. the amount of power dissipated in the chip could approach 18w under worst-case conditions. this amount of power will cause die temperature to rise until the circuit enters thermal figure 4. snap-back current limiting vc src common v ee vc snk v C filter v + 12v en v cc isnk isrc sense C sense + tsd out +in v in lt1970a C12v Cin r s 1 r l 1970a f04 r g 10k r f 10k r3 2.55k r2 39.2k r1 54.9k i max 500ma C500ma 50ma 0 i out i low v cc t3 33
tt3 s i max v cc t 3]]3
<3 3]]3
>tt3 s i low shutdown. while the thermal shutdown feature prevents damage to the circuit, normal operation is impaired. thermal design of the lt1970a operating environment is essential to getting maximum utility from the circuit. the first concern for thermal management is minimizing the heat which must be dissipated. the separate power pins v + and v C can be a great aid in minimizing on-chip power. the output pin can swing to within 1.0v of v + or v C even under maximum output current conditions. using separate power supplies, or voltage regulators, to set v + and v C to their minimum values for the required output swing will minimize power dissipation. the supplies v cc and v ee may also be reduced to a minimal value, but these supply pins do not carry high currents, and the power saving is much less. v cc and v ee must be greater than the maximum output swing by 1.5v or more.
lt1970a 14 1970afa applications information when v C and v + are provided separately from v cc and v ee , care must be taken to ensure that v C and v + are always less than or equal to the main supplies in magnitude. protection schottky diodes may be required to ensure this in all cases, including power on/off transients. operation with reduced v + and v C supplies does not affect any performance parameters except maximum output swing. all dc accuracy and ac performance specifications guaranteed with v cc = v + and v ee = v C are still valid with the reduced output signal swing range. heat sinking the power dissipated in the lt1970a die must have a path to the environment. with 100c/w thermal resistance in free air with no heat sink, the package power dissipation is limited to only 1w. the 20-pin tssop package with exposed copper underside is an efficient heat conductor if it is effectively mounted on a pc board. thermal resis- tances as low as 40c/w can be obtained by soldering the bottom of the package to a large copper pattern on the pc board. for operation at 85c, this allows up to 1.625w of power to be dissipated on the lt1970a. at 25c operation, up to 3.125w of power dissipation can be achieved. the pc board heat spreading copper area must be connected to v ee . figure 5 shows examples of pcb metal being used for heat spreading. these are provided as a reference for what might be expected when using different combina- tions of metal area on different layers of a pcb. these examples are with a 4-layer board using 1oz copper on each layer. the most effective layers for spreading heat are those closest to the lt1970a junction. soldering the exposed thermal pad of the tssop package to the board produces a thermal resistance from junction-to-case of approximately 3c/w. as a minimum, the area directly beneath the package on all pcb layers can be used for heat spreading. however, limiting the area to that of the metal heat sinking pad is not very effective. expanding the area on various layers significantly reduces the overall thermal resistance. the addition of vias (small 13 mil holes which fill during pcb plating) connecting all layers of metal also helps reduce the operating temperature of the lt1970a. these are also shown in figure 5. it is important to note that the metal planes used for heat sinking are connecting electrically to v ee . these planes must be isolated from any other power planes used in the pcb design. another effective way to control the power amplifier operat- ing temperature is to use airflow over the board. airflow can significantly reduce the total thermal resistance as also shown in figure 5. driving reactive loads capacitive loads the lt1970a is much more tolerant of capacitive loading than most operational amplifiers. in a worst-case con- figuration as a voltage follower, the circuit is stable for capacitive loads less than 2.5nf. higher gain configurations improve the c load handling. if very large capacitive loads are to be driven, a resistive decoupling of the amplifier from the capacitive load is effective in maintaining stability and reducing peaking. the current sense resistor, usually connected between the output pin and the load can serve as a part of the decoupling resistance. inductive loads load inductance is usually not a problem at the outputs of operational amplifiers, but the lt1970a can be used as a high output impedance current source. this condition may be the main operating mode, or when the circuit enters a protective current limit mode. just as load capacitance degrades the phase margin of normal op amps, load inductance causes a peaking in the loop response of the feedback controlled current source. the inductive load may be caused by long lead lengths at the amplifier output. if the amplifier will be driving inductive loads or long lead lengths (greater than 4 inches) a 500pf capacitor from the sense C pin to the ground plane will cancel the inductive load and ensure stability.
lt1970a 15 1970afa applications information figure 5. examples of pcb metal used for heat dissipation. driver package mounted on top layer. heat sink pad soldered to top layer metal. metal areas drawn to scale of package size still air v ja tssop 100 c/w tssop 50 c/w tssop 45 c/w package top layer 2nd layer 3rd layer bottom layer 1970a f05a airflow (linear feet per minute, lfpm) C50 C60 reduction in v ja (%) C30 C10 0 C40 C20 200 400 600 800 1970a f05b 1000 100 0 300 500 typical reduction in v ja with laminar air?ow over the device 700 900 % reduction relative to v ja in still air
lt1970a 16 1970afa applications information figure 6. current modulation of a magnetic transducer vc src common v ee vc snk v C filter v + 12v en v cc isnk isrc sense C sense + tsd out d2 1n4001 c1 500pf r1 95.3k lt1634-2.5 +in 5v v in 0v lt1970a C12v Cin 12v 5v sourcing sinking 2.5v r s 1 500ma magnetic transducer 1970a f06 d1 1n4001 figure 7. digitally controlled analog pin driver vc src common v ee vc snk v C filter v + 18v r6 3k 10f 0.1f en v cc isnk isrc sense C sense + tsd out +in r2 10.2k r1 3.4k 0v 5v apply load drive optional test pin on/off control hi-z lt1970a C18v 10f 0.1f sense Cin r s 1 force test pin load 1970a f07 r4 10.2k v cc v ref 5v clr dac a dac b c s /ld sck di dac c dac d r3 3.4k ltc1664 quad 10-bit dac decoder 3-wire serial interface + r5 3k + v out = 15v i source(max) = C4ma to C500ma 15v code c C code d 1024 () t$0%&# t3 s i sink(max) = 4ma to 500ma t$0%&" t3 s
lt1970a 17 1970afa applications information figure 6 shows the lt1970a driving an inductive load with a controlled amount of current. this load is shown as a generic magnetic transducer, which could be used to create and modulate a magnetic field. driving the current limit control inputs directly forces a current through the load that could range up to 2mhz in modulation. clamp diodes are added to protect the lt1970a output from large inductive flyback potentials caused by rapid di/dt changes. supply bypassing the lt1970a can supply large currents from the power supplies to a load at frequencies up to 4mhz. power supply impedance must be kept low enough to deliver these currents without causing supply rails to droop. low esr capacitors, such as 0.1f or 1f ceramics, located close to the pins are essential in all applications. when large, high speed transient currents are present additional capacitance may be needed near the chip. check supply rails with a scope and if signal related ripple is seen on the supply rail, increase the decoupling capacitor as needed. to ensure proper start-up biasing of the lt1970a, it is recommended that the rate of change of the supply volt- ages at turn-on be limited to be no faster than 6v/s. application circuit ideas the digitally controlled analog pin driver is shown in figure 7. all of the control signals are provided by an lt c ? 1664 quad, 10-bit dac by way of a 3-wire serial interface. the lt1970a is configured as a simple differ- ence amplifier with a gain of 3. this gain is required to produce 15v from the 0v to 5v outputs from dacs c and d. to provide voltage headroom, the supplies for the lt1970a are set to the maximum value of 18v. as 18v is the absolute maximum rating of supply voltage for the lt1970a, care must be taken to not allow the supply voltage to increase. dacs a and b separately control the sinking and sourcing current limit to the load over the range of 4ma to 500ma. an optional on/off control for the pin driver using the enable input is shown. if always enabled the enable pin should be tied to v cc . in some applications it may be necessary to know what the current into the load is at any time. figure 8 shows an lt1787 high side current sense amplifier monitoring the current through sense resistor r s . the lt1787 is biased from the v ee supply to accommodate the common mode input range of 10v. the sense resistor is scaled down to provide a 100mv maximum differential signal to the current sense amplifier to preserve linearity. the lt1880 amplifier provides gain and level shifting to produce a 0v to 5v output signal (2.5v dc 5mv/ma) with up to 1khz full-scale bandwidth. an a/d converter could then digi- tize this instantaneous current reading to provide digital feedback from the circuit. the lt1970a is just as easy to use as a standard opera- tional amplifier. basic amplification of a precision reference voltage creates a very simple bench dc power supply as shown in figure 9. the built-in power stage produces an adjustable 0v to 25v at 4ma to 100ma of output current. voltage and current adjustments are derived from the lt1634-5 5v reference. the output current capability is 500ma, but this supply is restricted to 100ma for power dissipation reasons. the worst-case output voltage for maximum power dissipated in the lt1970a output stage occurs if the output is shorted to ground or set to a voltage near zero. limiting the output current to 100ma sets the maximum power dissipation to 3w. to allow the output to range all the way to 0v, an ltc1046 charge pump inverter is used to develop a C5v supply. this produces a negative rail for the lt1970a which has to sink only the quiescent current of the amplifier, typically 7ma. using a second lt1970a, a 0v to 12v dual tracking power supply is shown in figure 10. the midpoint of two 10k resistors connected between the + and C outputs is held at 0v by the lt1881 dual op amp servo feedback loop. to maintain 0v, both outputs must be equal and opposite in polarity, thus they track each other. if one output reaches current limit and drops in voltage, the other output fol- lows to maintain a symmetrical + and C voltage across a common load. again, the output current limit is less than the full capability of the lt1970a due to thermal reasons. separate current limit indicators are used on each lt1970a because one output only sources current and the other only sinks current. both devices can share the same thermal shutdown indicator, as the output flags can be ored together.
lt1970a 18 1970afa applications information figure 8. sensing output current vc src common v ee vc snk v C filter v + 12v en v cc isnk isrc sense C sense + tsd out +in v cc 0v to 1v lt1970a C12v Cin r s 0.2 r load 1970a f08 r g r f v s C v ee 20k bias C12v C12v r1 60.4k r4 255k v out 2.5v 5mv/ma 1khz full current bandwidth r2 10k r3 20k v s + lt1787 C + lt1880 12v C12v 0v to 5v a/d optional digital feedback figure 9. simple bench power supply vc src current limit adjust common v ee vc snk v C filter v + en v cc isnk isrc sense C sense + tsd out c2 10f c1 10f r g 2.55k lt1634-5 +in lt1970a C5v Cin r s 1 r5 5.49k 30v dc load fault v out 0v to 25v 4ma to 100ma c3 10f gnd 1970a f09 + + + ltc1046 r f 10.2k r3 10k r4 10k output voltage adjust r1 2.1k r2 40k
lt1970a 19 1970afa applications information figure 10. dual tracking bench power supply vc src common v ee vc snk r5 13k v C filter v + 15v r6 18.2k r7 3k en v cc isnk isrc sense C sense + tsd out Cin lt1970a C15v r11 10k 15v c1 1f C15v +in r s1 1 +out current limit thermal fault r8 3k 0.1 10f r13 25.5k ground optional symmetry adjust 100 + c2 10f +out 0v to 12v 4ma to 150ma Cout 0v to C12v 4ma to 150ma 1970a f10 + vc src common v ee vc snk r14 10.7k v C filter v + 15v r15 3k en v cc isnk isrc sense C sense + tsd out Cin lt1970a C15v +in r s2 1 Cout current limit to tsd pin of +out c3 10f r10 10k 1% 10f 0.1f + + C + C + r12 10k 1/2 lt1881 1/2 lt1881 r9 10k 1% v out adjust current limit adjust r1 6.19k r2 10k r4 10k lt1634-5 r3 23.2k 5v ref 18v
lt1970a 20 1970afa vc src common r4 49.9k 15v C15v reverse forward r2 10k v ee vc snk v C filter v + 15v en v cc isnk isrc sense C sense + tsd out +in lt1970a C15v Cin r s 1 12v dc motor tach feedback 3v/1000rpm gnd 1970a f11 c1 1f r5 49.9k r3 1.2k r1 1.2k ov to 5v torque/stall current control figure 11. simple bidirectional dc motor speed controller applications information another simple linear power amplifier circuit is shown in figure 11. this uses the lt1970a as a linear driver of a dc motor with speed control. the ability to source and sink the same amount of output current provides for bidirectional rotation of the motor. speed control is managed by sensing the output of a tachometer built on to the motor. a typi- cal feedback signal of 3v/1000rpm is compared with the desired speed-set input voltage. because the lt1970a is unity-gain stable, it can be configured as an integrator to force whatever voltage across the motor as necessary to match the feedback speed signal with the set input signal. additionally, the current limit of the amplifier can be ad- justed to control the torque and stall current of the motor. for reliability, a feedback scheme similar to that shown in figure 4 can be used. assuming that a stalled rotor will generate a current limit condition, the stall current limit can be significantly reduced to prevent excessive power dissipation in the motor windings. for motor speed control without using a tachometer, the circuit in figure 12 shows an approach. using the enable feature of the lt1970a, the drive to the motor can be removed periodically. with no drive applied, the spinning motor presents a back emf voltage proportional to its rotational speed. the lt1782 is a tiny rail-to-rail amplifier with a shutdown pin. the amplifier is enabled during this interval to sample the back emf voltage across the motor. this voltage is then buffered by one-half of an lt1638 dual op amp and used to provide the feedback to the lt1970a integrator. when re-enabled the lt1970a will adjust the drive to the motor until the speed feedback voltage, com- pared to the speed-set input voltage, settles the output to a fixed value. a 0v to 5v signal for the motor speed input controls both rotational speed and direction. the other half of the lt1638 is used as a simple pulse oscillator to control the periodic sampling of the motor back emf. figure 13 shows how easy it is to boost the output current of the lt1970a. this 5a power stage uses complemen- tary external n- and p-channel mosfets to provide the additional current. the output stage power supply inputs, v + and v C , are used to provide gate drive as needed. with higher output currents, the sense resistor r cs , is reduced in value to maintain the same easy current limit control. this class b power stage is intended for dc and low frequency, <1khz, applications as crossover distortion becomes evident at higher frequencies. figure 13 shows some optional resistor dividers between the output connections and the current sense inputs. they are required only if the load of this power stage is removed or at a very low current level. large power devices with no load on them can saturate and pull the output voltage very close to the power supply rails. the current sense amplifiers operate properly with input voltages at least 1v away from the v cc and v ee supply rails. in boosted current applications, it may be necessary to attenuate the maximum output voltage levels by 1v before connecting to the sense input pins. this only slightly deceases the current limit thresholds.
lt1970a 21 1970afa applications information figure 12. simple bidirectional dc motor speed controller without a tachometer vc src com v ee vc snk v C filter v + fault/stall r3 2k 12v en v cc isnk isrc sense C sense + tsd out +in lt1970a C12v 12v C12v 12v 12v C12v Cin r s 1 12v dc motor 1970a f12 c1 4.7 f r15 100 c2 0.01 f shdn r14 10k ov to 5v torque/stall current control r2 20k r1 10k r4 100k r5 120k r7 10k r12 10k r13 10k r8 20k r9 20k r10 82.5k c3 0.1 f d1 1n4148 d2 1n4148 C12v r11 9.09k C + C + C + r6 49.9k 1/2 lt1638 1/2 lt1638 lt1782 5v 0v motor speed control rev fwd stop 1f 2.5v at 10ma
lt1970a 22 1970afa package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe20 (ca) tssop rev i 0211 0.09 C 0.20 (.0035 C .0079) 0 s C 8 s 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8910 11 12 14 13 6.40 C 6.60* (.252 C .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 t 0.05 0.65 bsc 4.50 t 0.10 6.60 t 0.10 1.05 t 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation ca
lt1970a 23 1970afa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 06/12 corrected d1, d2 orientation in block diagram changed supply voltage in figure 12 10 21
lt1970a 24 1970afa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0612 rev a ? printed in usa related parts applications information part number description comments lt1010 fast 150ma power buffer 20mhz bandwidth, 75v/s slew rate lt1206 250ma/60mhz current feedback amplifier shutdown mode, adjustable supply current LT1210 1.1a/35mhz current feedback amplifier stable with c l = 10,000pf lt1999 high voltage bidirectional current sense amplifier C5v to 80v input voltage range figure 13. a v = C 1 amplifier with discrete power devices to boost output current to 5a v cc v ee enable v C vc src vc snk sense C common sense + v + out +in r1 1k r g 2.2k r f 2.2k * * ** r cs 0.1 5w r5 100 r4 100 lt1970a Cin load 1970a f13 current limit control voltage 0v to 5v v cc 15v v ee C15v v in 10f irf9530 irf530 0.1f 0.1f 10f r3 100 *optional, see text r2 100

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